Parity mechanism

• PCI uses the PAR signal to maintain even parity across most signals.
• Rule:
  • If the number of “1” bits during the address/data phase is odd,
  • The master sets PAR so the total becomes even.

Error detection

• The target device checks the received data + PAR.
• If parity doesn’t match (not even), an error is detected.
• Note: Parity only detects errors if an odd number of bits are corrupted.

Data phase error (recoverable)

• If an error occurs during data transfer, the device asserts PERR# (Parity Error).
• Usually recoverable → e.g., just retrying the transaction (like re-reading memory) may succeed.
• Handled in software, since PCI doesn’t have automatic recovery.

Address phase error (serious)

• If an error occurs during the address phase, the address is corrupted.
• This is not recoverable, because:
  • The system can’t know what the corrupted address became.
  • The wrong device(s) may have responded.
• In this case, SERR# (System Error) is asserted.

System response to SERR#

• Typically invokes the system error handler.
• In older PCs:
  • Both PERR# and SERR# were connected to the South Bridge error logic.
  • This triggered an NMI (Non-Maskable Interrupt) to the CPU.
  • Often the system simply halted → leading to the infamous “Blue Screen of Death.”